Department of Information and Communications Engineering School of Engineering Tokyo Institute of Technology
Welcome to the Circuits and System Laboratory (Islam Laboratory).
Islam Lab was established in April 2024 to advance the circuits and systems field,
focusing on CMOS analog and mixed-signal integrated circuits.
We aim to find innovative circuit theories and techniques that fuse physics, analog, and digital strategies.
We emphasize beauty and elegance.
We want to develop original ideas and new interpretations rather than increase papers.
We want to work with bright students who can enjoy their development during the research process.
We encourage students to become independent and apply themselves fully.
We work closely with the students in developing their writing, communication and presentation skills.
We encourage to think out of the box in the group.
It is challenging to do something different from others.
It may take some time, but it is so fulfilling and satisfying in the end.
We are hiring enthusiastic and bright graduate students to work on different projects.
Contact us if you want to join my group or do collaborative research.
Please visit the recruit page for details.
Digital LDOs are gaining attention for their operation with small output capacitance. Adaptive sampling with a large frequency scaling ratio is required for fast transient response with low-power operation. Furthermore, the design of a fluctuation detector to deal with large load steps is important. This letter describes an adaptive-sampling digital LDO with a built-in clock generator and fluctuation detector based on statistical comparator selection. Statistical comparator selection utilizes offset voltage variation to realize stable implicit references. We apply order statistics for run-time calibration. Our proposed LDO fabricated in a commercial 65 nm low-power CMOS process operates from 0.6 to 1.2 V and achieves a maximum current efficiency of 99.99 %. The transient FoM is 0.25 ps.
J-14
TCAS
Low-Power Design of Digital LDO With Non-linear Symmetric Frequency Generation
This brief proposes a digital LDO (Low DropOut regulator) with a built-in non-linear VCO (Voltage Controlled Oscillator) to achieve both the fast transient response and low power operation. This on-chip VCO generates a clock signal whose frequency is a non-linear symmetric function of the output voltage error. Here, we propose a design technique to realize the symmetric frequency generation with low power consumption. We demonstrate a design example of LDO using our proposed technique in a commercial 65 nm low-power CMOS process. We evaluate the LDO using transistor-level simulation using HSPICE. It achieves 0.03-11 \muA of quiescent current with an input voltage range of 0.6-1.2 V and an average current efficiency of 99.68 % across 50\times load range.
J-11
SSCL
A 6.4 nW 1.7% Relative Inaccuracy CMOS Temperature Sensor Utilizing Sub-Thermal Drain Voltage Stabilization and Frequency-Locked Loop
A 6.4 nW 1.7% relative inaccuracy (R-IA) CMOS sub-thermal drain voltage-based temperature sensor is proposed. The proposed stabilized sub-thermal drain voltage current generator achieves a highly linear PTAT output without nonlinearity fitting or post-fabrication trimming and increases the accuracy of the sensor. A combination of the current generator and a frequency-locked loop relaxes the tradeoff between power and temperature stability of the current-to-frequency converter and achieves supply voltage-independent operation. Measured results of the prototype fabricated in a 65-nm CMOS process show that the proposed temperature sensor has a -1.0/+0.7 °C inaccuracy ( = R-IA of 1.7%) while achieving a resolution of 75 mK over a temperature range of -30 °C to 70 °C. The line sensitivity of the sensor is 2.8 °C/V.
J-10
JSSC
An 11-nW CMOS temperature-to-digital converter utilizing
sub-threshold current at sub-thermal drain voltage
A fully integrated CMOS temperature-to-digital converter
utilizing MOSFETs in the sub-threshold region is proposed. The
temperature-to-digital converter achieves the ultra-low power
operation required for Internet of Things (IoT) nodes. The
proposed principle takes the ratio of the sub-threshold currents
of two nMOSFETs whose drain voltages are maintained well above
and well below the thermal voltage, respectively. The proposed
circuit implementation of the temperature-to-digital converter
achieves ultra-low power consumption of 11 nW at room
temperature of 25 °C. Measurement results of the proposed
temperature sensor fabricated in a 180-nm CMOS process show
-0.9/+1.2 °C peak-to-peak inaccuracy over a temperature range of
-20 °C to 80 °C after a two-point calibration while achieving a
resolution of 145 mK.
J-7
TSM
Statistical Analysis and Modeling of Random Telegraph Noise Based on Gate Delay Measurement
Mahfuzul
Islam, Tatsuya
Nakai
, and Hidetoshi
Onodera
IEEE Transactions on Semiconductor Manufacturing, Aug 2017
We propose a characterization methodology for random telegraph noise (RTN) based on gate delay measurement. To convert delay change to MOSFET threshold voltage fluctuation, \DeltaVT, a topology-reconfigurable ring oscillator is utilized. We discuss the issue of detecting RTN-induced discrete fluctuations in the delay and develop a kernel density-based method to detect the fluctuations. Characterization results of several RTN properties from a test chip fabricated in a 65 nm bulk process are presented. Particular focus is given on the suitable distribution to present RTN-induced overall \DeltaVT distribution and its gate area dependency. The results show that lognormal distribution is better at representing the total \DeltaVT distribution. RTN-induced delay fluctuation of 40% has been observed for a single gate under weak inversion operation. Local process variation and RTN amplitude are found to be uncorrelated. The proposed methodology is thus suitable for characterizing RTN of devices operating under switching condition.
J-5
JSSC
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring
Mahfuzul
Islam, Jun
Shiomi
, Tohru
Ishihara
, and Hidetoshi
Onodera
Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature variation. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. A compact reconfigurable inverter topology is proposed to implement the monitor circuit. The compact and digital nature of the inverter enables cell-based design, which will reduce design costs. Measurement results from a 65 nm test chip show the validity of the proposed circuit. For a 124 sample size for both of the nMOSFET and pMOSFET, the monitor area is 4500 \mum2 and active power consumption is 76 nW at 0.8 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as dynamic energy and thermal management, testing and post-silicon tuning.
J-2
TSM
Inhomogeneous Ring Oscillator for Within-Die Variability and RTN Characterization
This paper discusses the concept of an inhomogeneous structure for a ring oscillator (RO) to enhance the delay effect of a particular inverter stage. The frequency of the proposed inhomogeneous structure becomes a strong function of the inhomogeneous stage; thus, the variability becomes directly visible. With careful design of the inhomogeneous stage, the RO frequency can be made sensitive to a small set of transistors for characterizing transistor-by-transistor variability. Performance sensitivities of the transistors are enhanced more than 100 times that of other transistors in the RO. The proposed ROs are embedded into a 65-nm RO-array test structure, and it is verified that these ROs are highly sensitive to within-die local variability and random telegraph noise (RTN). The within-die local variability is then successfully decomposed into threshold voltage and gate length variations. Several characteristics of RTN have been successfully extracted with the proposed structure. The proposed structure is thus very useful for observation, characterization and modeling of static and dynamic transistor variations during switching operation.
J-1
TSM
Variation-sensitive monitor circuits for estimation of global process parameter variation
This paper proposes a set of monitor circuits to estimate global process variations in post-silicon. Ring oscillators (ROs) are chosen as monitor circuits where ROs are designed to have enhanced sensitivities to process variations. The proposed technique extracts process parameter variations from RO outputs. An iterative estimation method is also developed to estimate variations correctly under the presence of nonlinearity in RO outputs to process variations. Simulation results show that the proposed circuits are robust against uncertainties such as measurement error. A test chip in a 65-nm process has been fabricated to validate the circuits. Process parameter variations are successfully estimated and verified by applying body bias to the chip. The proposed technique can be used for post-silicon compensation techniques and model-to-hardware correlation.