This chapter deals with random telegraph noise (RTN) under switching operation. We measured and modeled RTN by using ring oscillator-based (RO-based) test chips. They were fabricated in three different processes of 65 nm bulk, 65 nm FDSOI, and 40 nm bulk. Measurements are performed for ROs of different topology, gate width, and stage number under different supply voltage, substrate bias, and temperature. Measurement results reveal valuable insights into the impact of RTN on the reliability of logic circuits. We have also shown the variability change according to gate width, stage number, and supply voltage. We presented design methodology of a test structure so as to extract RTN parameters, which is used to develop a Verilog-AMS model.
@book{rtn2020book,title={Noise in Nanoscale Semiconductor Devices, Chapter: Random Telegraph Noise Under Switching Operation},chapter={Random Telegraph Noise Under Switching Operation},author={Kobayashi, Kazutoshi and Islam, Mahfuzul and Matsumoto, Takashi and Kishida, Ryo},year={2020},pages={285--333},publisher={Springer},}
B-1
Springer
Dependable Embedded Systems, Chapter: Monitor Circuits for Cross-Layer Resiliency
Cross-layer resiliency has become a critical deciding factor for any successful product. This chapter focuses on monitor circuits that are essential in realizing the cross-layer resiliency. The role of monitor circuits is to establish a bridge between the hardware and other layers by providing information about the devices and the operating environment in run-time. This chapter explores delay-based monitor circuits for design automation with the existing cell-based design methodology. The chapter discusses several design techniques to monitor parameters of threshold voltage, temperature, leakage current, critical delay, and aging. The chapter then demonstrates a reconfigurable architecture to monitor multiple parameters with small area footprint. Finally, an extraction methodology of physical parameters is discussed for model-hardware correlation. Utilizing the cell-based design flow, delay-based monitors can be placed inside the target digital circuit and thus a better correlation between monitor and target circuit behavior can be realized.
@book{monitor2020book,title={Dependable Embedded Systems, Chapter: Monitor Circuits for Cross-Layer Resiliency},author={Islam, Mahfuzul and Onodera, Hidetoshi},year={2020},pages={385--407},publisher={Springer},}
Journal/Conference Papers
2024
J-19
SSC-L
A Fully Integrated Digital LDO With Adaptive Sampling and Statistical Comparator Selection
Shun
Yamaguchi
, Takashi
Hisakado
, Osami
Wada
, and Mahfuzul
Islam
Digital LDOs are gaining attention for their operation with small output capacitance. Adaptive sampling with a large frequency scaling ratio is required for fast transient response with low-power operation. Furthermore, the design of a fluctuation detector to deal with large load steps is important. This letter describes an adaptive-sampling digital LDO with a built-in clock generator and fluctuation detector based on statistical comparator selection. Statistical comparator selection utilizes offset voltage variation to realize stable implicit references. We apply order statistics for run-time calibration. Our proposed LDO fabricated in a commercial 65 nm low-power CMOS process operates from 0.6 to 1.2 V and achieves a maximum current efficiency of 99.99 %. The transient FoM is 0.25 ps.
@article{Yamaguchi2024-km,title={A Fully Integrated Digital LDO With Adaptive Sampling and Statistical Comparator Selection},author={Yamaguchi, Shun and Hisakado, Takashi and Wada, Osami and Islam, Mahfuzul},journal={IEEE Solid-state Circuits Letters},publisher={Institute of Electrical and Electronics Engineers (IEEE)},year={2024}}
J-18
T-SLDM
Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups
Takehiro
Kitamura
, Takashi
Hisakado
, Osami
Wada
, and Mahfuzul
Islam
IPSJ Transactions on System and LSI Design Methodology, 2024
Statistical element selection has been proposed to solve the offset voltage variation problem for a flash ADC. A calibration method based on order statistics has been proposed for statistical selection that does not require offset voltage measurement. This paper presents a design methodology of flash ADC with such calibration using multiple comparator groups. We validate our proposal with measurement results from test chips fabricated in a commercial 65nm general-purpose process. Measurement results confirm that rank-based comparator selection achieves a reference-free ADC. Compared to the baseline ADC, where only one group of comparators is used, the ADC with three groups significantly increases the linearity and input range under the same power consumption. As no reference voltage and DACs are required, the proposed ADC design will help realize ADCs in advanced process nodes with lower power consumption.
@article{Kitamura2024-py,title={Design of Reference-free Flash {ADC} With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups},author={Kitamura, Takehiro and Hisakado, Takashi and Wada, Osami and Islam, Mahfuzul},journal={IPSJ Transactions on System and LSI Design Methodology},volume={17},pages={36--43},year={2024},}
2023
J-17
NOLTA
Global stabilization for nonlinear two-port characteristics of bidirectional DC/DC converter and its application to peer-to-peer energy transfer
A global stabilization method for the conversion characteristics of a bidirectional DC/DC converter and its application in peer-to-peer energy transfer systems is described. Peer-to-peer energy transfer is a control strategy in which the supply and load cooperate to transmit power, and it requires the global operation of the converter. According to the power relation, the bidirectional DC/DC converter has two equilibrium points. To realize global stability, a unique equilibrium point is achieved by eliminating the untargeted equilibrium point using the power relationship between the ports. Global stability is realized by setting feedback gains to converge globally to this equilibrium point. The experimental results demonstrate the global stability of the proposed method when applied to a stand-alone system and a peer-to-peer energy transfer system.
@article{Yamamoto2023-yp,title={Global stabilization for nonlinear two-port characteristics of bidirectional {DC/DC} converter and its application to peer-to-peer energy transfer},author={Yamamoto, Kenta and Hisakado, Takashi and Islam, Mahfuzul and Wada, Osami},journal={Nonlinear Theory and Its Applications, IEICE},volume={14},number={2},pages={292--307},year={2023},}
J-16
JJAP
Wide-range and low supply dependency MOSFET-based temperature sensor utilizing statistical properties of scaled MOSFETs
Shinichi
Ota
, Mahfuzul
Islam, T
Hisakado
, and O
Wada
We present a MOSFET-based temperature sensing method capable of high-accuracy temperature estimation across a wide temperature range while having a low supply voltage dependency. Existing MOSFET-based sensors, while capable of low-power operation, suffer from low sensing accuracy and a narrow sensing range. The proposed method utilizes per-MOSFET parameter variations seen in scaled CMOS processes. By measuring a statistical parameter of sub-threshold drain currents, we can extract a complimentary temperature value. To prove the feasibility of our method, we measure six chips fabricated with a commercial 65 nm process. The proposed method achieves a sensing accuracy of −0.54/ + 0.43 °C within a temperature range of −20 °C to 120 °C at a supply voltage of 1.2 V. In addition, the proposed method has a worst-case supply dependency of only 1.8 °C V−1 at 20 °C.
@article{Ota2023-nt,title={Wide-range and low supply dependency {MOSFET-based} temperature sensor utilizing statistical properties of scaled {MOSFETs}},author={Ota, Shinichi and Islam, Mahfuzul and Hisakado, T and Wada, O},journal={Japanese Journal of Applied Physics},volume={62},month=feb,year={2023},}
J-15
TEMC
Single-Conductor Transmission-Line Model for Bent Wire Structures
Daiki
Tashiro
, Kana
Sameshima
, Takashi
Hisakado
, Mahfuzul
Islam, and Osami
Wada
IEEE Transactions on Electromagnetic Compatibility, Oct 2023
A bend in a single-conductor line is a primary cause of radiation associated with the antenna mode; conversely, the radiation is fed back, resulting in attenuation and distortion of the current waveform. Despite being a fundamental phenomenon, its dynamics have not been sufficiently characterized. Therefore, this study presents a single-conductor transmission-line model for bent wire structures comprising multiple straight elements by using the local variables of charge per-unit-length and current along a thin conductor. The proposed model is validated over a wide frequency range using the method of moments. The total charge and current distributions that an external field induces on a bent structure are classified into three components: the scattering source distribution, traveling wave corresponding to the Sommerfeld mode, and radiation reaction. These components suggest an overall field-line coupling process: initially, an external electromagnetic field induces a scattering current in the structure, which in turn drives traveling and radiation-reaction currents at the ends, resulting in propagation along the line accompanied by radiation losses. The presented model is advantageous for designing electromagnetic phenomena corresponding to antennas and metamaterials and for addressing electromagnetic interference problems using passive circuit elements. A case study that makes use of the precise and descriptive model is included to predict the field emissions associated with the antenna mode around a bend.
@article{Tashiro2023-ja,title={{Single-Conductor} {Transmission-Line} Model for Bent Wire Structures},author={Tashiro, Daiki and Sameshima, Kana and Hisakado, Takashi and Islam, Mahfuzul and Wada, Osami},journal={IEEE Transactions on Electromagnetic Compatibility},publisher={IEEE},volume={65},number={5},pages={1432--1445},month=oct,year={2023},}
C-53
A-SSCC
An Adaptive-Sampling Digital LDO with Statistical Comparator Selection Achieving 99.99% Maximum Current Efficiency and 0.25ps FoM in 65nm
Shun
Yamaguchi
, Takashi
Hisakado
, Osami
Wada
, and Mahfuzul
Islam
In IEEE Asian Solid-State Circuits Conference (A-SSCC) , Nov 2023
Attention to digital LDO has been increasing due to their low-power and wide-voltage-range operation. For fine-grain power control of an SoC (System-on-a-Chip), LDOs with small output capacitance and low quiescent current are required. A typical synchronous Digital LDO with a fixed clock frequency suffers from power and transient response trade-off. To achieve a fast transient response with low quiescent current, techniques such as adaptive sampling, event-driven control, and level-triggered asynchronous loop are proposed [1]–[7]. Asynchronous LDOs often utilize delay or logical threshold voltage for droop detection. However, the droop detection voltage and the quantization resolution deviate largely under different voltages. Furthermore, delay and logical threshold voltages are highly susceptible to PVT variation, and the control algorithm tends to become complex [2]. In the case of synchronous LDOs, adaptive sampling with the help of a built-in VCO (Voltage Controlled Oscillator) can achieve both low power and fast transient response. Several droop detectors are proposed to boost a synchronous LDO’s transient response [3]–[7]. These droop detectors require additional reference voltages that poses a significant challenge in integrating such LDOs with small areas and power. Furthermore, comparators with upsized transistors or preamplifiers are employed to realize low offset voltage, increasing kick-back noise or quiescent current. Because of high kickback noise, low output impedance reference generators are required causing power overhead [4]. Thus, we identify stable reference voltages as the key issue in realizing low-power LDOs with variable output voltage.
@inproceedings{Yamaguchi2023-mr,title={An {Adaptive-Sampling} Digital {LDO} with Statistical Comparator Selection Achieving 99.99\% Maximum Current Efficiency and 0.25ps {FoM} in 65nm},booktitle={{IEEE} Asian {Solid-State} Circuits Conference ({A-SSCC})},author={Yamaguchi, Shun and Hisakado, Takashi and Wada, Osami and Islam, Mahfuzul},publisher={IEEE},pages={1--3},month=nov,year={2023},}
C-52
ASP-DAC
A Fully Synchronous Digital LDO with Built-in Adaptive Frequency Modulation and Implicit Dead-Zone Control
This paper proposes a synchronous digital LDO with adaptive clocking and dead-zone control without additional reference voltages. A test chip fabricated in a commercial 65 nm CMOS general-purpose (GP) process achieves 580x frequency modulation with 99.9% maximum efficiency at 0.6V supply.
@inproceedings{Yamaguchi2023-ve,title={A Fully Synchronous Digital {LDO} with Built-in Adaptive Frequency Modulation and Implicit {Dead-Zone} Control},booktitle={IEEE/ACM 28th Asia and South Pacific Design Automation Conference},author={Yamaguchi, Shun and Islam, Mahfuzul and Hisakado, Takashi and Wada, Osami},publisher={Association for Computing Machinery},pages={186--187},series={ASPDAC '23},month=jan,year={2023},address={New York, NY, USA},location={Tokyo, Japan}}
C-51
ASP-DAC
Demonstration of Order Statistics Based Flash ADC in a 65nm Process
This paper presents measurement results of a flash ADC that utilizes offset voltages as references. To operate the minimum number of comparators, we select the target comparators based on the rankings of the offset voltage. We present performance improvement by tuning offset voltage distribution using multiple comparator groups under the same power. A test chip in a commercial 65 nm GP process demonstrates the ADCs at 1 GS/s operation.
@inproceedings{Islam2023-ec,title={Demonstration of Order Statistics Based Flash {ADC} in a 65nm Process},booktitle={IEEE/ACM 28th Asia and South Pacific Design Automation Conference},author={Islam, Mahfuzul and Kitamura, Takehiro and Hisakado, Takashi and Wada, Osami},publisher={Association for Computing Machinery},pages={188--189},series={ASPDAC '23},month=jan,year={2023},address={New York, NY, USA},location={Tokyo, Japan}}
C-50
ICMTS
Measurement of Temperature Effect on Comparator Offset Voltage Variation
Yuma
Iwata
, Takehiro
Kitamura
, and Mahfuzul
Islam
In IEEE International Conference on Microelectronic Test Structure , Mar 2023
Comparator offset voltage often limits the perfor-mance of a system. This paper demonstrates a measurement circuit of offset voltage variation. The digital nature of the circuit allows complete automation to enable high-volume measurement. We evaluate the temperature effect on offset voltage for 255 near-minimum size comparators fabricated in a commercial 65 nm general-purpose process. Detailed evaluation of offset voltage under a wide temperature range reveals that the temperature drift coefficient of offset voltage is a few mVs over 100 o C. We also reveal that asymmetric sizing will cause large drifts in offset voltage, in the order of several tens of mV over 100 o C. Thus, offset calibration circuits as well as circuits utilizing offset voltage variation need to take sufficient measures.
@inproceedings{Iwata2023-oz,title={Measurement of Temperature Effect on Comparator Offset Voltage Variation},booktitle={IEEE International Conference on Microelectronic Test Structure},author={Iwata, Yuma and Kitamura, Takehiro and Islam, Mahfuzul},publisher={IEEE},pages={1--6},month=mar,year={2023},}
C-49
ICPE
Real-time Temperature Estimation of SiC MOSFETs Using Gate Voltage at Zero-current Switching for Inverter Applications
Raul R
Rodriguez G.
, Mahfuzul
Islam, Takashi
Hisakado
, and Osami
Wada
In 11th International Conference on Power Electronics and ECCE Asia , May 2023
Nowadays, temperature monitoring has gained great focus to improve their reliability. For SiC MOSFETs, thermal sensitive electrical parameters (TSEP) are being widely investigated because of their ease of measurement and implementation. However, implementing such methods faces several critical problems, such as the ringing noise in the gate voltage waveform due to parasitic inductances and large output currents. This work proposes a gate voltage measurement method for inverter applications utilizing a zero-current switching (ZCS) period. We also propose slowing the gate switching speed during zero-current switching to obtain a stable gate voltage waveform for accurate estimation. We validate our proposed method by measuring the gate voltage waveforms of three commercial SiC devices through the double pulse test. Utilizing the plateau voltage, we demonstrate that temperature sensing can be performed within 5 % of error up to 100 °C temperature.
@inproceedings{Rodriguez_G2023-ee,title={Real-time Temperature Estimation of {SiC} {MOSFETs} Using Gate Voltage at Zero-current Switching for Inverter Applications},booktitle={11th International Conference on Power Electronics and {ECCE} Asia},author={Rodriguez G., Raul R and Islam, Mahfuzul and Hisakado, Takashi and Wada, Osami},publisher={IEEE},pages={1355--1360},month=may,year={2023},}
C-48
NEWCAS
CMOS Temperature Sensor Utilizing Gate-length-based Threshold Voltage Modulation
We propose a leakage-current ratio-based temperature-to-digital converter that does not require any reference or bias generation. Our proposed principle is based on threshold voltage modulation by gate length. Taking the current ratio of two MOSFETs whose gate lengths are tuned appropriately, we obtain a PTAT (proportional-to-absolute temperature) characteristic. We have designed a relaxation oscillator-based digital converter in a commercial 65 nm general-purpose process. Monte Carlo simulation demonstrates that the sensing error of the sensor is -0.6/+0.4°C whereas the supply voltage dependency is only 3.4°C/V for ten samples.
@inproceedings{Islam2023-jx,title={{CMOS} Temperature Sensor Utilizing Gate-length-based Threshold Voltage Modulation},booktitle={21st {IEEE} Interregional {NEWCAS} Conference ({NEWCAS})},author={Islam, Mahfuzul and Harada, Shogo and Hisakado, Takashi and Wada, Osami},publisher={IEEE},pages={1--5},month=jun,year={2023},}
2022
J-14
TCAS
Low-Power Design of Digital LDO With Non-linear Symmetric Frequency Generation
This brief proposes a digital LDO (Low DropOut regulator) with a built-in non-linear VCO (Voltage Controlled Oscillator) to achieve both the fast transient response and low power operation. This on-chip VCO generates a clock signal whose frequency is a non-linear symmetric function of the output voltage error. Here, we propose a design technique to realize the symmetric frequency generation with low power consumption. We demonstrate a design example of LDO using our proposed technique in a commercial 65 nm low-power CMOS process. We evaluate the LDO using transistor-level simulation using HSPICE. It achieves 0.03-11 \muA of quiescent current with an input voltage range of 0.6-1.2 V and an average current efficiency of 99.68 % across 50\times load range.
@article{Yamaguchi2022-ud,google_scholar_id={WbkHhVStYXYC},title={{Low-Power} Design of Digital {LDO} With Non-linear Symmetric Frequency Generation},author={Yamaguchi, Shun and Islam, Mahfuzul and Hisakado, Takashi and Wada, Osami},journal={IEEE Transactions on Circuits and Systems II: Express Briefs},publisher={ieeexplore.ieee.org},pages={1--1},year={2022},}
J-13
IEICE
Order Statistics Based Low-power Flash ADC with On-chip Comparator Selection
High-speed flash ADCs are useful in high-speed applications such as communication receivers. Due to offset voltage variation in the sub-micron processes, the power consumption and the area increase significantly to suppress variation. As an alternative to suppressing the variation, we have developed a flash ADC architecture that selects the comparators based on offset voltage ranking for reference generation. Specifically, with the order statistics as a basis, our method selects the minimum number of comparators to obtain …
@article{Kitamura2022-er,google_scholar_id={Tiz5es2fbqcC},title={Order Statistics Based Low-power Flash {ADC} with On-chip Comparator Selection},author={Kitamura, Takehiro and Islam, Mahfuzul and Hisakado, Takashi and Wada, Osami},journal={IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences},publisher={jstage.jst.go.jp},volume={advpub},pages={2021KEP0007},year={2022},}
J-12
JJAP
On-chip leakage current variation measurement using external-reference-free current-to-time conversion for densely placed MOSFETs
This paper proposes a time-domain leakage current measurement circuit that uses an external-reference-free current-to-time conversion. Our proposed current-to-time converter (CTC) utilizes a dual inverter-based conversion to provide a stable reference. We share the CTC among the devices under test (DUTs) for accurate characterization of variation. Our CTC, along with a tree-based switch structure, allows us to densely place and route the DUT transistors using a cell-based design flow similar to a digital circuit design. We demonstrate our circuit by measuring subthreshold leakage currents of 256 minimum sized nMOSFETs in a 65 nm bulk low-power CMOS process. We could successfully extract the variations in subthreshold coefficient and subthreshold leakage current at different temperatures. Our circuit is also robust to supply voltage fluctuation making the circuit suitable for accurate characterization of MOSFET parameters for subthreshold operation.
@article{Islam2022-og,title={On-chip leakage current variation measurement using external-reference-free current-to-time conversion for densely placed {MOSFETs}},author={Islam, Mahfuzul and Harada, Shogo},journal={Japanese Journal of Applied Physics},publisher={IOP Publishing},volume={61},number={SC},pages={SC1056},month=feb,year={2022},language={en}}
C-47
SSDM
Wide temperature- and voltage-range temperature sensing utilizing statistical property of sub-threshold MOSFET current
Shinichi
Ota
, Mahfuzul
Islam, Takashi
Hisakado
, and Osami
Wada
In International Conference on Solid State Devices and Materials , Sep 2022
@inproceedings{Oota20220-ja,author={Ota, Shinichi and Islam, Mahfuzul and Hisakado, Takashi and Wada, Osami},title={Wide temperature- and voltage-range temperature sensing utilizing statistical property of sub-threshold MOSFET current},booktitle={International Conference on Solid State Devices and Materials},pages={788--789},month=sep,year={2022}}
C-46
NOLTA
Global Stabilization for Nonlinear Two-Port Characteristics of Bidirectional DC/DC Converter
This paper describes the nonlinear two-port characteristics of bidirectional DC/DC converters and its two different operating points. The nonlinearity of the two-port characteristics affects global stability. We show that global stabilization of the bidirectional DC/DC converter can be achieved by a feedback method based on the nonlinear two-port characteristics. Experiment confirms the proposed feedback method to realize global stability.
@inproceedings{Yamamoto2022-dv,title={Global Stabilization for Nonlinear {Two-Port} Characteristics of Bidirectional {DC/DC} Converter},booktitle={{IEICE} Proceedings Series,},author={Yamamoto, Kenta and Hisakado, Takashi and Islam, Mahfuzul and Wada, Osami},publisher={The Institute of Electronics, Information and Communication Engineers},year={2022},}
C-45
NEWCAS
Performance Improvement of Order Statistics Based Flash ADC Using Multiple Comparator Groups
Due to offset voltage variation, power consumption increases significantly to ensure sufficient performance of flash ADCs. As a solution, statistical selection of comparators based on the order of offset voltages has been proposed. This method achieves at-speed on-chip calibration without the need for analog measurements. To increase the linearity and SNDR under the same power consumption, this paper proposes to use multiple comparator groups with different sizing to tune a distribution of offset voltage. We design and fabricate two ADCs, one with only single comparator group and the other with three comparator groups, in a 65 nm bulk general-purpose process. We confirm the ADC operations at a 1 GS/s and validate order statistic based comparator selection. We then confirm INL improvement by using multiple groups under the same number of total comparators.
@inproceedings{Kitamura2022-ql,title={Performance Improvement of Order Statistics Based Flash {ADC} Using Multiple Comparator Groups},booktitle={20th {IEEE} Interregional {NEWCAS} Conference ({NEWCAS})},author={Kitamura, Takehiro and Islam, Mahfuzul and Hisakado, Takashi and Wada, Osami},pages={1--4},month=jun,year={2022},}
C-44
ICMTS
Homogeneous Ring Oscillator with Staggered Layout for Gate-level Delay Characterization
Misaki
Udo
, Mahfuzul
Islam, and Hidetoshi
Onodera
In IEEE 34th International Conference on Microelectronic Test Structures , Mar 2022
Ring oscillator circuits are useful for the characterization of MOS transistors under switching operation. Accurate characterization of per-gate variation becomes difficult when the ring oscillator consists of many stages or contains heterogeneity. We propose a homogeneous ring oscillator structure with a staggered layout for the accurate characterization of per-gate characteristics. Using a header transistor instead of a NAND gate for oscillation control, our proposed structure can realize a 3-stage RO where the three stages have equal delay contributions. Measurement results from a 65 nm test chip confirm our proposed structure for gate-level characterization.
@inproceedings{Udo2022-dk,title={Homogeneous Ring Oscillator with Staggered Layout for Gate-level Delay Characterization},booktitle={{IEEE} 34th International Conference on Microelectronic Test Structures},author={Udo, Misaki and Islam, Mahfuzul and Onodera, Hidetoshi},publisher={IEEE},pages={1--6},month=mar,year={2022},}
2021
C-43
A-SSCC
A process scalable voltage-reference-free temperature sensor utilizing MOSFET threshold voltage variation
This paper proposes a temperature sensing mechanism that utilizes the threshold voltage variation of MOSFETs. The sensor statistically selects two MOSFETs with an appropriate threshold voltage difference to obtain a current ratio proportional to absolute temperature. As the threshold voltage difference acts as a voltage reference, a wide-voltage operation becomes possible without the need for an accurate voltage reference. The sensor sorts the current values during the start-up and automatically selects the two MOSFETs based on predefined rank values. A cell-based implementation of the sensor in a 65 nm bulk low-power CMOS process shows a peak-to-peak inaccuracy of -0.5/+1.4^∘\mathrm C after a 2-point calibration over 0∼100^∘\mathrm C, and a line sensitivity of 14^∘\mathrm C/V over 0.8 1.2 V operation.
@inproceedings{Harada2021-av,title={A process scalable voltage-reference-free temperature sensor utilizing {MOSFET} threshold voltage variation},booktitle={{IEEE} Asian {Solid-State} Circuits Conference},author={Harada, Shogo and Islam, Mahfuzul and Hisakado, Takashi and Wada, Osami},pages={1--3},month=nov,year={2021},}
C-42
IOLTS
On-chip leakage current variation measurement using reference-free current-to-time conversion
Mahfuzul
Islam, and Shogo
Harada
In International Conference on Solid State Devices and Materials , Sep 2021
This paper proposes a time-domain leakage current measurement circuit that uses an external-reference-free currentto-time conversion. Furthermore, we share the current-to-time converter (CTC) among the devices under test (DUTs). With our CTC along with a tree-based switch structure allows us to place and route the DUT transistors using a cell-based design flow. Thus, current variations of scaled MOSFETs under a cell-based design environment becomes feasible. We demonstrate our circuit by measuring subthreshold leakage currents of 256 minimum sized nMOSFETs in a 65 nm bulk CMOS process.
@inproceedings{Islam2021-dc,author={Islam, Mahfuzul and Harada, Shogo},title={On-chip leakage current variation measurement using reference-free current-to-time conversion},booktitle={International Conference on Solid State Devices and Materials},month=sep,year={2021},pages={694--695},}
C-41
IOLTS
CDF Distance Based Statistical Parameter Extraction Using
Nonlinear Delay Variation Models
Kensuke
Murakami
, Mahfuzul
Islam, and Hidetoshi
Onodera
In IEEE 27th International Symposium on On-Line Testing
and Robust System Design , Jun 2021
This paper proposes a parameter extraction method by comparing
the cumulative distribution functions (CDF) between measurement
and model-based estimation. We propose a nonlinear delay
variation model for fast Monte Carlo simulation to obtain CDFs.
We demonstrate the validity of our method by extracting
within-die and random telegraph noise induced threshold voltage
variations using measured data obtained from a 65 nm test
structure. Our proposed method can accurately extract the
statistical parameters and can reproduce the measured delay
variations by simulation.
@inproceedings{Murakami2021-bm,title={{CDF} Distance Based Statistical Parameter Extraction Using
Nonlinear Delay Variation Models},booktitle={{IEEE} 27th International Symposium on {On-Line} Testing
and Robust System Design},author={Murakami, Kensuke and Islam, Mahfuzul and Onodera, Hidetoshi},pages={1--6},month=jun,year={2021},}
C-40
ISQED
Flash ADC Utilizing Offset Voltage Variation With Order
Statistics Based Comparator Selection
High-speed flash ADCs are required for wireless communication
systems. However, the trade-off between area, power, and
linearity suffers severely by offset voltage variation in
sub-micron process. This paper proposes a flash ADC architecture
that utilizes the offset voltage variation to reduce area and
power consumption by eliminating reference generation. The
proposed architecture utilizes offset voltages as references by
selecting the appropriate comparators after an on-chip
calibration. The on-chip calibration is performed based on order
statistics that allows evaluating offset voltages in the
time-domain. We verify our proposed architecture by HSPICE
simulation based on a commercial 65 nm process. Our proposed
architecture realizes a 5-bit ADC with the power consumption of
less than 1 mW at 2 GS/s of operation, excluding the encoder.
@inproceedings{Kitamura2021-wu,title={Flash {ADC} Utilizing Offset Voltage Variation With Order
Statistics Based Comparator Selection},booktitle={22nd International Symposium on Quality Electronic Design},author={Kitamura, Takehiro and Islam, Mahfuzul and Hisakado, Takashi and Wada, Osami},pages={103--108},month=apr,year={2021},}
2020
J-11
SSCL
A 6.4 nW 1.7% Relative Inaccuracy CMOS Temperature Sensor Utilizing Sub-Thermal Drain Voltage Stabilization and Frequency-Locked Loop
A 6.4 nW 1.7% relative inaccuracy (R-IA) CMOS sub-thermal drain voltage-based temperature sensor is proposed. The proposed stabilized sub-thermal drain voltage current generator achieves a highly linear PTAT output without nonlinearity fitting or post-fabrication trimming and increases the accuracy of the sensor. A combination of the current generator and a frequency-locked loop relaxes the tradeoff between power and temperature stability of the current-to-frequency converter and achieves supply voltage-independent operation. Measured results of the prototype fabricated in a 65-nm CMOS process show that the proposed temperature sensor has a -1.0/+0.7 °C inaccuracy ( = R-IA of 1.7%) while achieving a resolution of 75 mK over a temperature range of -30 °C to 70 °C. The line sensitivity of the sensor is 2.8 °C/V.
@article{Someya2020-pg,google_scholar_id={dfsIfKJdRG4C},title={A 6.4 nW 1.7\% Relative Inaccuracy {CMOS} Temperature Sensor Utilizing {Sub-Thermal} Drain Voltage Stabilization and {Frequency-Locked} Loop},author={Someya, Teruki and Islam, Mahfuzul and Okada, Kenichi},journal={IEEE Solid-state Circuits Letters},publisher={Institute of Electrical and Electronics Engineers (IEEE)},volume={3},pages={458--461},year={2020},}
C-39
A-SSCC
A 6.4 nW 1.7% Relative Inaccuracy CMOS Temperature Sensor Utilizing Sub-Thermal Drain Voltage Stabilization and Frequency-Locked Loop
Teruki
Someya
, Mahfuzul
Islam, and Kenichi
Okada
In IEEE Asian Solid-State Circuits Conference , Apr 2020
@inproceedings{Someya2020-aj,google_scholar_id={dfsIfKJdRG4C},title={A 6.4 nW 1.7\% Relative Inaccuracy {CMOS} Temperature Sensor Utilizing {Sub-Thermal} Drain Voltage Stabilization and {Frequency-Locked} Loop},author={Someya, Teruki and Islam, Mahfuzul and Okada, Kenichi},booktitle={IEEE Asian Solid-State Circuits Conference},year={2020}}
C-38
NOLTA
Power Equalization of Peer-to-Peer Energy Transfer in Star Networks Using Broadcast from Reference Voltage Source
@inproceedings{Kawamoto2020,author={Kawamoto, Masaki and Hisakado, Takashi and Islam, Mahfuzul and Wada, Osami},title={Power Equalization of Peer-to-Peer Energy Transfer in Star Networks Using Broadcast from Reference Voltage Source},booktitle={International Symposium on Nonlinear Theory and Its Applications},month=nov,year={2020}}
C-37
SISPAD
Power Device Degradation Estimation by Machine Learning of Gate Waveforms
H
Yamasaki
, K
Miyazaki
, Y
Lo
, Mahfuzul
Islam, K
Hata
, T
Sakurai
, and M
Takamiya
In International Conference on Simulation of Semiconductor Processes and Devices , Sep 2020
The emitter resistance (RE), the junction temperature (TJ), the collector current (IC), and the threshold voltage (VTH) of power devices are key parameters that determine the reliability of power devices. Adding dedicated sensors to measure the key parameters, however, will increase the cost of the power converters. To solve the problem, power device degradation estimation methods by the machine learning of gate waveforms are proposed. Two methods are shown in this paper. First, in order to detect the bond wire lift-off of power devices, the estimation of the number of the connected bond wires using the linear regression of two feature points extracted from the gate waveforms of a SiC MOSFET is shown using SPICE simulations. Then, in order to detect the power device degradation, the estimation of R E, TJ, IC, and VTH using the convolutional neural network (CNN) with the gate waveforms of an IGBT for input is shown using both simulations and measurements.
@inproceedings{Yamasaki2020-st,title={Power Device Degradation Estimation by Machine Learning of Gate Waveforms},booktitle={International Conference on Simulation of Semiconductor Processes and Devices},author={Yamasaki, H and Miyazaki, K and Lo, Y and Islam, Mahfuzul and Hata, K and Sakurai, T and Takamiya, M},pages={335--338},month=sep,year={2020},}
C-36
METAMATERIALS
Excitation of the Light Line Mode with Metamaterials Composed of Parallel Conductors Based On Equivalent-Circuit Model Including Retarded Electromagnetic Coupling
This paper clarifies the characteristics of parallel conductors and the mechanism for the phenomenon at the light line. By analyzing parallel conductors with an equivalent circuit model including retardation, the singularity at the light line is clarified. Using this singularity, it is possible to excite the light line mode specifically and form a beam with a sharp directivity.
@inproceedings{Akimarul2020-kh,title={Excitation of the Light Line Mode with Metamaterials Composed of Parallel Conductors Based On {Equivalent-Circuit} Model Including Retarded Electromagnetic Coupling},booktitle={Fourteenth International Congress on Artificial Materials for Novel Wave Phenomena},author={Akimaru, Daisuke and Hisakado, Takashi and Islam, Mahfuzul and Wada, Osami},pages={291--293},month=sep,year={2020},}
C-35
ICMTS
Increased Delay Variability due to Random Telegraph Noise under Dynamic Back-gate Tuning
Dynamic back-gate voltage tuning is an effective technique for run-time optimization of energy consumption in an LSI. In this paper, we present our observation that variability due to RTN under back-gate voltage tuning increases significantly at low voltage operation. We investigate on the mechanism of the increase of variability and its impact on circuit performance using a ring oscillator based test chip fabricated in a 65 nm FDSOI process. Measurement results imply that additional care needs to be taken for circuits under dynamic voltage tuning.
@inproceedings{Udo2020-xn,title={Increased Delay Variability due to Random Telegraph Noise under Dynamic Back-gate Tuning},booktitle={{IEEE} 33rd International Conference on Microelectronic Test Structures},author={Udo, Misaki and Murakami, Kensuke and Islam, Mahfuzul and Onodera, Hidetoshi},pages={1--6},month=may,year={2020},}
2019
J-10
JSSC
An 11-nW CMOS temperature-to-digital converter utilizing
sub-threshold current at sub-thermal drain voltage
A fully integrated CMOS temperature-to-digital converter
utilizing MOSFETs in the sub-threshold region is proposed. The
temperature-to-digital converter achieves the ultra-low power
operation required for Internet of Things (IoT) nodes. The
proposed principle takes the ratio of the sub-threshold currents
of two nMOSFETs whose drain voltages are maintained well above
and well below the thermal voltage, respectively. The proposed
circuit implementation of the temperature-to-digital converter
achieves ultra-low power consumption of 11 nW at room
temperature of 25 °C. Measurement results of the proposed
temperature sensor fabricated in a 180-nm CMOS process show
-0.9/+1.2 °C peak-to-peak inaccuracy over a temperature range of
-20 °C to 80 °C after a two-point calibration while achieving a
resolution of 145 mK.
@article{Someya2019-lk,title={An 11-nW {CMOS} temperature-to-digital converter utilizing
sub-threshold current at sub-thermal drain voltage},author={Someya, Teruki and Islam, Mahfuzul and Sakurai, Takayasu and Takamiya, Makoto},journal={IEEE Journal of Solid-state Circuits},publisher={ieeexplore.ieee.org},volume={54},number={3},pages={613--622},month=mar,year={2019},google_scholar_id={pqnbT2bcN3wC}}
J-9
T-SLDM
Circuit Techniques for Device-Circuit Interaction toward Minimum
Energy Operation
Mahfuzul
Islam, and Hidetoshi
Onodera
IPSJ Transactions on System and LSI Design Methodology, Mar 2019
@article{Islam2019-rq,title={Circuit Techniques for {Device-Circuit} Interaction toward Minimum
Energy Operation},author={Islam, Mahfuzul and Onodera, Hidetoshi},journal={IPSJ Transactions on System and LSI Design Methodology},volume={12},pages={2--12},year={2019},}
C-34
NOLTA
Transients of Gyrator Network of Bidirectional AC/DC Converters in Peer-to-Peer Energy Transfer
A.K.M. Mahfuzul Islam
Nobuhiko Kawashima
, and Osami
Wada
In International Symposium on Nonlinear Theory and Its Applications , Dec 2019
@inproceedings{Kawashima2019,author={Nobuhiko Kawashima, Takashi Hisakado, A.K.M. Mahfuzul Islam and Wada, Osami},title={Transients of Gyrator Network of Bidirectional AC/DC Converters in Peer-to-Peer Energy Transfer},booktitle={International Symposium on Nonlinear Theory and Its Applications},month=dec,year={2019},pages={2-6}}
C-33
METAMATERIALS
Topological Tuning of a Dispersion Curve by Controlling Locations of Impurities with Equivalent Circuit Model
This paper describes a topological method for tuning dispersion curves by controlling locations of doped impurities in a periodic lattice. To find effective locations of impurities, we derive an equivalent circuit model for the structure of wired metallic spheres and topologically estimate the resonant frequencies by the graph Laplacian of the incident matrix. By using the topological perturbation of the Laplacian, we propose an algorithm to determine the locations of impurities automatically.
@inproceedings{Haegawa2019-mv,title={Topological Tuning of a Dispersion Curve by Controlling Locations of Impurities with Equivalent Circuit Model},booktitle={Thirteenth International Congress on Artificial Materials for Novel Wave Phenomena},author={Hasegawa, Akira and Hisakado, Takashi and Islam, Mahfuzul and Wada, Osami},pages={149--151},month=sep,year={2019},}
C-32
ICICDT
CNN-based Approach for Estimating Degradation of Power Devices by Gate Waveform Monitoring
Koutaro
Miyazaki
, Yang
Lo
, Mahfuzul
Islam, Katsuhiro
Hata
, Makoto
Takamiya
, and Takayasu
Sakurai
In International Conference on IC Design and Technology , Jun 2019
A Convolutional Neural Network (CNN) is applied to estimate the emitter resistance (R E ), the junction temperature (T J ), the collector current (I C ), and the threshold voltage (V TH ) of power devices just by monitoring the gate drive waveforms. R E , T J and I C are essential parameters for power device reliability. By using the detailed circuit simulation results for IGBT, it is shown that the above-mentioned four parameters can be estimated with the success rate more than 93% by the proposed AI-based approach for the first time. The measurement results also show that R E and I C are successfully estimated with the success rate >99%. The discussions are made on the success rate change depending on the resolution and the sampling rate of an A/D converter and the convolution filter kernel size.
@inproceedings{Miyazaki2019-kg,title={{CNN-based} Approach for Estimating Degradation of Power Devices by Gate Waveform Monitoring},booktitle={International Conference on {IC} Design and Technology},author={Miyazaki, Koutaro and Lo, Yang and Islam, Mahfuzul and Hata, Katsuhiro and Takamiya, Makoto and Sakurai, Takayasu},publisher={IEEE},pages={1--4},month=jun,year={2019},}
C-31
ICMTS
Effect of Logic Depth ad Switching Speed on Random Telegraph Noise Induced Delay Fluctuation
Mahfuzul
Islam, Ryota
Shimizu
, and Hidetoshi
Onodera
In IEEE 32nd International Conference on Microelectronic Test Structures , Mar 2019
We present measurement results of the effect of switching speed and logic depth on random telegraph noise (RTN) induced delay fluctuation using a test chip fabricated in a 65-nm Silicon-On- Thin-Buried-Oxide process. Measurement results reveal that the expected value of delay fluctuation decreases rapidly with the increase of logic depth. However, the delay fluctuation above 99th percentile is not strongly affected by logic depth. RTN-induced delay fluctuations are found to be not affected by the switching speed of logic gates. The measurement results provide useful insights into developing a statistical static timing analysis (SSTA) framework to asses the worst-case delay under the presence of RTN.
@inproceedings{Islam2019-oi,title={Effect of Logic Depth ad Switching Speed on Random Telegraph Noise Induced Delay Fluctuation},booktitle={{IEEE} 32nd International Conference on Microelectronic Test Structures},author={Islam, Mahfuzul and Shimizu, Ryota and Onodera, Hidetoshi},publisher={ieeexplore.ieee.org},pages={166--170},month=mar,year={2019},}
C-30
ISQED
Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits
Mahfuzul
Islam, Shinichi
Nishizawa
, Y
Matsui
, and Y
Ichida
In 20th International Symposium on Quality Electronic Design , Mar 2019
For a highly duty-cycled IoT device, the circuit spends most of the time in sleep mode. As a result, leakage-energy becomes the dominant energy consumption source. Therefore, circuit design to minimize the leakage-power has become a critical issue. The state-of-the-art standard-cell library is optimized for high-performance designs and is power-hungry. We show that choosing a suitable set of drive-strengths can reduce the leakage-energy by order magnitudes for highly duty-cycled devices. To realize the suitable set, cells with larger gate-lengths or stacked devices are essential although they increase cell area and gate capacitance. The holistic property of a standard-cell library ensures that a better circuit can be synthesized with the slow cells in the library. We have compared two libraries with one being “thin & dense” in its drive-strength varieties, while the other being fat and sparse. Synthesis results using ISCAS‘85 circuits show a maximum of 1/5 reduction of leakage-power with our proposed “fat & sparse” library than that with a conventional “thin & dense” library.
@inproceedings{Islam2019-ym,title={{Drive-Strength} Selection for Synthesis of {Leakage-Dominant} Circuits},booktitle={20th International Symposium on Quality Electronic Design},author={Islam, Mahfuzul and Nishizawa, Shinichi and Matsui, Y and Ichida, Y},pages={298--303},month=mar,year={2019},}
C-29
IRPS
Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring Oscillators
Mahfuzul
Islam, Ryota
Shimizu
, and Hidetoshi
Onodera
In IEEE International Reliability Physics Symposium , Mar 2019
We present measurement results of delay fluctuations induced by random telegraph noise (RTN) from 154k 7-stage ring oscillators (RO). Measurement results are obtained from test chips fabricated in a 65-nm Silicon-On-Thin-Buried-Oxide process. Measurement results reveal that RTN-induced frequency fluctuation which corresponds to the underlying threshold voltage deviation follows lognormal distribution up to 4.5σ. A maximum of 13.5% of delay fluctuation has been observed. Measurement results also reveal that the worst-case value including both of the static and dynamic variations is 14% larger than that where only the static variation is considered.
@inproceedings{Mahfuzul_Islam2019-ei,title={Analysis of Random Telegraph Noise ({RTN}) at {Near-Threshold} Operation by Measuring 154k Ring Oscillators},booktitle={{IEEE} International Reliability Physics Symposium},author={Islam, Mahfuzul and Shimizu, Ryota and Onodera, Hidetoshi},pages={1--6},month=mar,year={2019},}
2018
J-8
ACCESS
Feature Extraction, Performance Analysis and System Design Using the DU Mobility Dataset
Swapnil Sayan
Saha
, Shafizur
Rahman
, Miftahul Jannat
Rasna
, Tarek Bin
Zahid
, Mahfuzul
Islam, and Md Atiqur Rahman
Ahad
The University of Dhaka mobility data set (DU-MD) is a human action recognition (HAR) data set consisting of 10 classes and 5000 observations from 50 subjects recorded using wrist-mounted sensors embracing accelerometry. The data set exhibits sufficient statistical diversity in physiological parameters and a noteworthy correlation between similar activities with coveted quantitative and qualitative features, suitable for training machine learning models. On the other hand, the wrist-mounted approach parallels the future commercial scenarios. In this paper, we explore how the quantitative features of the DU-MD have been extracted and selected. Existing machine learning models used in HAR, in particular, support vector machines, ensemble of classifiers, and subspace K-nearest neighbours have been applied to our data set for activity and fall classification, with outcomes being compared with benchmark and similar data sets. With a HAR classification accuracy of 93%, fall detection accuracy of 97% and fall classification of 68.3%, quantitative performance metrics have either approached or outperformed other data sets, making this data set suitable for application in hardware-independent healthcare monitoring systems. Finally, we construct an algorithm with our data set based on performance metrics, and suggest some strategies for large-scale commercial implementation.
@article{Saha2018-mn,google_scholar_id={M05iB0D1s5AC},title={Feature Extraction, Performance Analysis and System Design Using the {DU} Mobility Dataset},author={Saha, Swapnil Sayan and Rahman, Shafizur and Rasna, Miftahul Jannat and Zahid, Tarek Bin and Islam, Mahfuzul and Ahad, Md Atiqur Rahman},journal={IEEE Access},publisher={ieeexplore.ieee.org},volume={6},pages={44776--44786},year={2018},}
C-28
ICCAD
PVT^2: Process, Voltage, Temperature and Time-dependent Variability in Scaled CMOS Process
Mahfuzul
Islam, and Hidetoshi
Onodera
In IEEE/ACM International Conference on Computer-Aided Design , Nov 2018
In addition to the conventional PVT (Process, Voltage and Temperature) variation, time-dependent current fluctuation such as random telegraph noise (RTN) poses a new challenge on VLSI reliability. In this paper, we show that compared with the static random variation, RTN amplitude of a particular device is not constant across supply voltages and temperatures. A device may show large RTN amplitude at one operating condition and small amplitude at another operating condition. As a result, RTN amplitude distribution becomes uncorrelated across a wide range of voltage and temperature. The emergence of uncorrelated distribution causes significant degradation of worst-case values. Analysis results based on variability models from a 65 nm silicon-on-insulator process show that uncorrelated RTN degrades the worst-case threshold voltage value significantly compared with that where RTN is not considered. Delay variation analysis shows that consideration of RTN in the statistical analysis have little impact at high supply voltage. However, at low voltage operation, RTN can degrade the worst-case value by more than 5%.
@inproceedings{Islam2018-kz,title={{PVT$^{2}$}: Process, Voltage, Temperature and Time-dependent Variability in Scaled {CMOS} Process},booktitle={{IEEE/ACM} International Conference on {Computer-Aided} Design},author={Islam, Mahfuzul and Onodera, Hidetoshi},publisher={IEEE Press},pages={1--6},month=nov,year={2018},}
C-27
PATMOS
Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage Variability
Mahfuzul
Islam, and Hidetoshi
Onodera
In 28th International Symposium on Power and Timing Modeling, Optimization and Simulation , Jul 2018
RTN induced threshold voltage distribution has a long tail that can degrade the worst-case distribution severely. In this paper, we analyze the effect of RTN on worst-case performance based on variability models extracted from a 65 nm silicon-on-thin-body low threshold voltage process. Monte Carlo based simulation results reveal that with the lowering of supply voltage, RTN can degrade the worst-case delay by more than 10 % when the number of critical paths is 10. The worst-case delay degradation can go as high as 100 % if the critical path number increases to 100. Because of the RTN induced threshold voltage fluctuation, several outliers appear at near/sub-threshold operation. Considering RTN amplitude can increase at weak-inversion operation, low-voltage operation needs careful consideration of RTN.
@inproceedings{Islam2018-zk,title={{Worst-Case} Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage Variability},booktitle={28th International Symposium on Power and Timing Modeling, Optimization and Simulation},author={Islam, Mahfuzul and Onodera, Hidetoshi},publisher={ieeexplore.ieee.org},pages={140--146},month=jul,year={2018},}
C-26
ICIEV
DU-MD: An Open-Source Human Action Dataset for Ubiquitous Wearable Sensors
Swapnil Sayan
Saha
, Shafizur
Rahman
, Miftahul Jannat
Rasna
, Mahfuzul
Islam, and Md Atiqur
Rahman Ahad
In 7th International Conference on Informatics, Electronics and Vision , Jun 2018
Human Action Recognition (HAR) in healthcare amongst senior citizens focuses on remote surveillance, healthcare monitoring and fall detection. The wearable approach, in particular, wrist-mounted sensors for HAR is most favorable when qualitative characteristics, parameter complexities and market projections are considered. Machine learning models for Activities of Daily Living (ADL) / fall detection require large, hardware-independent and comprehensive ADL datasets exhibiting statistical variance and closeness to real life cases. However, there is a lack of public motion traces filling in all necessary obligations. In this context, the University of Dhaka (DU) Mobility Dataset (MD) was built using 25 subjects (out of 50) with 10 ADL (7 basic ADL and 3 falls), amounting to 2500 (out of a final 5000) training sets using a single wrist-mounted wearable sensor. Some existing public databases have been compared extensively and assembly of the wearable sensor using the recently developed UTokyo Trillion Node Engine Project is illustrated. Statistical tests have been carried out to ensure diversity whilst accuracy of the dataset using existing statistical mechanisms have been acknowledged. Promising diversity and accuracy make this dataset suitable for use in wrist-mounted healthcare monitoring systems.
@inproceedings{Saha2018-zo,google_scholar_id={ZHo1McVdvXMC},title={{DU-MD}: An {Open-Source} Human Action Dataset for Ubiquitous Wearable Sensors},booktitle={7th International Conference on Informatics, Electronics and Vision},author={Saha, Swapnil Sayan and Rahman, Shafizur and Rasna, Miftahul Jannat and Islam, Mahfuzul and Rahman Ahad, Md Atiqur},publisher={ieeexplore.ieee.org},pages={567--572},month=jun,year={2018},}
C-25
CICC
A 13nW temperature-to-digital converter utilizing sub-threshold MOSFET operation at sub-thermal drain voltage
A new principle of temperature sensing based on a sub-threshold MOSFET operation at sub-thermal drain voltage is proposed. The proposed external-reference-free temperature-to-digital converter with on-chip proportional-to-absolute-temperature (PTAT) digital output achieves the lowest power consumption of 13nW at 0.8V. The proposed principle takes the ratio of two sub-threshold currents with different drain voltages. The principle is implemented using op-amp-free current generators and relaxation oscillator based current-to-frequency converters for ultra-low power operation. Measurement results from 8 chips fabricated in a 180-nm CMOS process achieve 110mK resolution and -0.7/+1.3°C inaccuracy over a temperature range of -20°C to 80°C.
@inproceedings{Someya2018-gr,title={A 13nW temperature-to-digital converter utilizing sub-threshold {MOSFET} operation at sub-thermal drain voltage},booktitle={{IEEE} Custom Integrated Circuits Conference},author={Someya, Teruki and Islam, Mahfuzul and Sakurai, Takayasu and Takamiya, Makoto},publisher={ieeexplore.ieee.org},pages={1--4},month=apr,year={2018},}
C-24
ICMTS
Measurement of temperature effect on random telegraph noise induced delay fluctuation
Mahfuzul
Islam, Masashi
Oka
, and Hidetoshi
Onodera
In IEEE International Conference on Microelectronic Test Structures , Mar 2018
We present detailed measurement results of temperature effect on Random Telegraph Noise (RTN) induced delay fluctuation using a test chip fabricated in a 65-nm Silicon-On-Thin-Buried-Oxide process. Skewed ring oscillators (ROs) are used to characterize pMOFSET and nMOSFET specific RTN effects. Distributions of overall threshold fluctuation of a device have been extracted such that the simulated delay distribution matches with the measured delay distribution. For worst-case delay prediction, circuit analysis with ∆ντdistribution model for low temperature is necessary. Estimation results reveal that RTN amplitude decreases slightly with the increase of temperature. However, low correlation of 0.3 to 0.4 has been observed across temperatures ranging from 0 °C to 80 °C for delay paths. We find appearing and disappearing of traps across the temperature range causing the low correlation. Low correlation poses challenges in realizing robust runtime performance compensation techniques such as replica critical path based delay compensation.
@inproceedings{Islam2018-wc,title={Measurement of temperature effect on random telegraph noise induced delay fluctuation},booktitle={{IEEE} International Conference on Microelectronic Test Structures},author={Islam, Mahfuzul and Oka, Masashi and Onodera, Hidetoshi},publisher={ieeexplore.ieee.org},pages={210--215},month=mar,year={2018},}
2017
J-7
TSM
Statistical Analysis and Modeling of Random Telegraph Noise Based on Gate Delay Measurement
Mahfuzul
Islam, Tatsuya
Nakai
, and Hidetoshi
Onodera
IEEE Transactions on Semiconductor Manufacturing, Aug 2017
We propose a characterization methodology for random telegraph noise (RTN) based on gate delay measurement. To convert delay change to MOSFET threshold voltage fluctuation, \DeltaVT, a topology-reconfigurable ring oscillator is utilized. We discuss the issue of detecting RTN-induced discrete fluctuations in the delay and develop a kernel density-based method to detect the fluctuations. Characterization results of several RTN properties from a test chip fabricated in a 65 nm bulk process are presented. Particular focus is given on the suitable distribution to present RTN-induced overall \DeltaVT distribution and its gate area dependency. The results show that lognormal distribution is better at representing the total \DeltaVT distribution. RTN-induced delay fluctuation of 40% has been observed for a single gate under weak inversion operation. Local process variation and RTN amplitude are found to be uncorrelated. The proposed methodology is thus suitable for characterizing RTN of devices operating under switching condition.
@article{Islam2017-xl,google_scholar_id={O3NaXMp0MMsC},title={Statistical Analysis and Modeling of Random Telegraph Noise Based on Gate Delay Measurement},author={Islam, Mahfuzul and Nakai, Tatsuya and Onodera, Hidetoshi},journal={IEEE Transactions on Semiconductor Manufacturing},publisher={ieeexplore.ieee.org},volume={30},number={3},pages={216--226},month=aug,year={2017},}
J-6
JETCAS
Programmable Neuron Array Based on a 2-Transistor Multiplier Using Organic Floating-Gate for Intelligent Sensors
Artificial neurons are introduced for local data processing in a large area sensor device, thereby reducing multiple sensor outputs to 1-bit digital output. To reduce the area overhead and layout complexity due to the artificial neuron array, a 2-transistor multiplier using organic floating-gate pFET is proposed. Each artificial neuron has multiple organic floating-gate pFETs embedded in it. A virtual scalable floating-gate based memory architecture is realized for selective programming of each floating-gate pFET. Threshold voltage tuning is utilized to realize both of the positive and the negative weight values for a neuron. A flexible interface pressure monitoring device with pressure-sensitive rubber sheet is developed for pressure ulcer prevention to show the feasibility of our concept. A 50 mm2 organic sheet integrating 2\times2 neuron array is fabricated with 2-V organic CMOS transistors. Selective floating-gate programming and neuron operation are successfully demonstrated.
@article{Mahfuzul_Islam2017-nv,title={Programmable Neuron Array Based on a 2-Transistor Multiplier Using Organic {Floating-Gate} for Intelligent Sensors},author={Islam, Mahfuzul and Hamamatsu, Masamune and Yokota, Tomoyuki and Lee, Sunghoon and Yukita, Wakako and Takamiya, Makoto and Someya, Takao and Sakurai, Takayasu},journal={IEEE Journal on Emerging and Selected Topics in Circuits and Systems},publisher={ieeexplore.ieee.org},volume={7},number={1},pages={81--91},month=mar,year={2017},}
C-23
VARI
Supply Voltage Effect on Random Telegraph Noise Induced Delay Variation
Mahfuzul
Islam, and Hidetoshi
Onodera
In IEEE/ACM Workshop on Variability Modeling and Characterization , Nov 2017
@inproceedings{Islam2017Supply,author={Islam, Mahfuzul and Onodera, Hidetoshi},title={Supply Voltage Effect on Random Telegraph Noise Induced Delay Variation},booktitle={IEEE/ACM Workshop on Variability Modeling and Characterization},month=nov,year={2017}}
C-22
PATMOS
Effect of supply voltage on random telegraph noise of transistors under switching condition
Mahfuzul
Islam, and Hidetoshi
Onodera
In 27th International Symposium on Power and Timing Modeling, Optimization and Simulation , Sep 2017
For efficient design of digital circuits operating under wide range of voltage voltages, RTN model incorporating the dependencies of both the gate area and supply voltage are required. In this paper, we characterize the delay distributions due to RTN under different supply voltages. The delay distributions are then converted to threshold voltage distributions by statistical analysis. Measurement results from a 65 nm Silicon-on-Thin-Buried-Oxide high performance process reveal that threshold voltage distribution remains almost the same across the supply voltages of 0.4 V to 1.0 V. Furthermore, nMOSFET and pMOSFET ∆Υτdistributions are also estimated to be identical. However, low correlation has been observed between the RTN amplitudes across the supply voltages which is a concern for testing and post-silicon tuning methods.
@inproceedings{Islam2017-qd,title={Effect of supply voltage on random telegraph noise of transistors under switching condition},booktitle={27th International Symposium on Power and Timing Modeling, Optimization and Simulation},author={Islam, Mahfuzul and Onodera, Hidetoshi},publisher={ieeexplore.ieee.org},pages={1--8},month=sep,year={2017},}
C-21
ICMTS
A statistical modeling methodology of RTN gate size dependency based on skewed ring oscillators
Mahfuzul
Islam, Tatsuya
Nakai
, and Hidetoshi
Onodera
In IEEE International Conference of Microelectronic Test Structures , Mar 2017
This paper proposes a statistical modeling methodology of RTN (Random Telegraph Noise) gate size dependency utilizing skewed ring oscillator (RO) structures. An iterative characterization flow is developed to estimate RTN induced threshold distribution of each gate sizes of pMOSFET and nMOSFET independently. The skewed RO based test structure was fabricated in a 65 nm SOTB (Silicon On Thin Body) process. It is observed that Lognormal distribution represents RTN induced delay distribution well. RTN model of gate size dependency is then developed and validated using the measured data. Model based delay distribution estimation and measurement match well. The proposed extraction methodology is thus suitable for estimating RTN of transistors with arbitrary gate size. The model helps reliability and worst case analysis of digital circuits where transistors of various gate sizes are used.
@inproceedings{Islam2017-rz,title={A statistical modeling methodology of {RTN} gate size dependency based on skewed ring oscillators},booktitle={IEEE International Conference of Microelectronic Test Structures},author={Islam, Mahfuzul and Nakai, Tatsuya and Onodera, Hidetoshi},publisher={ieeexplore.ieee.org},pages={1--6},month=mar,year={2017},}
2016
C-20
SID
Sensor and Circuit Solutions for Organic Flexible Electronics
This paper describes several sensor and circuit solutions for organic flexible electronic devices. Organic field effect transistors (OFET) enable low-cost, high-flexibility and large-area which can be utilized to implement smart sensors. These sensors can be in contact with the physical objects of any shape. Furthermore, as the devices are very light and flexible, they can even be placed in contact with the human skins. However, design of organic flexible circuits poses great challenges because of several intrinsic properties of organic materials. Thus, newer circuit techniques need to be adopted for robust operation. We give an overview of various sensor and circuit techniques developed in our research group along with other literature reports.
@inproceedings{Islam2016,author={Islam, Mahfuzul and Fuketa, Hiroshi and Ishida, Koichi and Yokota, Tomoyuki and Sekitani, Tsuyoshi and Takamiya, Makoto and Someya, Takao and Sakurai, Takayasu},title={Sensor and Circuit Solutions for Organic Flexible Electronics},booktitle={Society for Information Display Symposium Digest of Technical Papers},month=may,year={2016},pages={629--632}}
C-19
ICMTS
Statistical analysis and modeling of Random Telegraph Noise based on gate delay variation measurement
Mahfuzul
Islam, Tatsuya
Nakai
, and Hidetoshi
Onodera
In IEEE International Conference on Microelectronic Test Structures , May 2016
@inproceedings{Islam2016-sa,title={Statistical analysis and modeling of Random Telegraph Noise based on gate delay variation measurement},booktitle={IEEE International Conference on Microelectronic Test Structures},year={2016},pages={82--87},author={Islam, Mahfuzul and Nakai, Tatsuya and Onodera, Hidetoshi},keywords={Delays;Logic gates;Integrated circuit modeling;Transistors;Inverters;MOSFET circuits;Solid modeling},}
C-18
ASP-DAC
On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations
Mahfuzul
Islam, and Hidetoshi
Onodera
In 21st Asia and South Pacific Design Automation Conference , Jan 2016
Aggressive technology scaling and strong demand for lowering supply voltage impose a serious challenge in achieving robust and energy-efficient circuit operation. This paper first overviews on device-circuit interactions to enable cross-layer resiliency, and energy optimization. We show that the ability to monitor and control device and circuit characteristics not only increase energy-efficiency by more than 20% but also relax the severe design constraints, which were required because of the uncertainties of variability. We then demonstrate two proof-of-concept circuits in a 65 nm process to show variability resiliency and energy optimization with local body biasing.
@inproceedings{Islam2016-tb,title={On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations},booktitle={21st Asia and South Pacific Design Automation Conference},author={Islam, Mahfuzul and Onodera, Hidetoshi},publisher={ieeexplore.ieee.org},pages={403--409},month=jan,year={2016},}
2015
J-5
JSSC
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring
Mahfuzul
Islam, Jun
Shiomi
, Tohru
Ishihara
, and Hidetoshi
Onodera
Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature variation. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. A compact reconfigurable inverter topology is proposed to implement the monitor circuit. The compact and digital nature of the inverter enables cell-based design, which will reduce design costs. Measurement results from a 65 nm test chip show the validity of the proposed circuit. For a 124 sample size for both of the nMOSFET and pMOSFET, the monitor area is 4500 \mum2 and active power consumption is 76 nW at 0.8 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as dynamic energy and thermal management, testing and post-silicon tuning.
@article{Islam2015-sw,google_scholar_id={hMod-77fHWUC},title={{Wide-Supply-Range} {All-Digital} Leakage Variation Sensor for {On-Chip} Process and Temperature Monitoring},author={Islam, Mahfuzul and Shiomi, Jun and Ishihara, Tohru and Onodera, Hidetoshi},journal={IEEE Journal of Solid-state Circuits},publisher={ieeexplore.ieee.org},volume={50},number={11},pages={2475--2490},month=nov,year={2015},}
C-17
VARI
Characterization of Gate Width Dependency on Random Telegraph Noise using Reconfigurable Ring Oscillator for Compact Statistical Modeling
Mahfuzul
Islam, Tatsuya
Nakai
, and Hidetoshi
Onodera
In IEEE/ACM Workshop on Variability Modeling and Characterization , Nov 2015
@inproceedings{Islam2015Characterization,author={Islam, Mahfuzul and Nakai, Tatsuya and Onodera, Hidetoshi},title={Characterization of Gate Width Dependency on Random Telegraph Noise using Reconfigurable Ring Oscillator for Compact Statistical Modeling},booktitle={IEEE/ACM Workshop on Variability Modeling and Characterization},month=nov,year={2015}}
C-16
ICMTS
Sensitivity-independent extraction of Vth variation utilizing log-normal delay distribution
Mahfuzul
Islam, and Hidetoshi
Onodera
In IEEE International Conference on Microelectronic Test Structures (ICMTS) , Mar 2015
We propose an area-efficient and low-cost extraction methodology of Vth variation which utilizes the exponential relationship of gate delay to Vth variation. The exponential relationship is achieved by operating the DUT in the weak inversion region. Utilizing a previously proposed pass-gate based topology-reconfigurable ring oscillator, the weak inversion operation of a specific gate is achieved while maintaining a much higher supply voltage for the overall circuit. Area-efficiency is achieved by altering the individual gate topology and measuring for each topology. Based on a pass-gate inserted inverter delay model, the relationship of delay variation to Vth variation is expressed using the body effect and DIBL coefficients. Thus, the proposed method does not require any sensitivity calculation. Vth variation is then extracted from the measured delay distributions directly. A test chip containing three different sizes of DUTs are fabricated in a 65-nm bulk CMOS process. Vth variation of nMOSFET and pMOSFET for three different DUT sizes are successfully extracted. The methodology is suitable for low-cost, area-efficient and all-digital measurement of Vth variation.
@inproceedings{Mahfuzul_Islam2015-lz,title={Sensitivity-independent extraction of Vth variation utilizing log-normal delay distribution},booktitle={IEEE International Conference on Microelectronic Test Structures (ICMTS)},author={Islam, Mahfuzul and Onodera, Hidetoshi},publisher={ieeexplore.ieee.org},pages={212--217},month=mar,year={2015},}
C-15
ISQED
Energy reduction by built-in body biasing with single supply voltage operation
Energy-efficiency has become the driving force of today’s LSI industry. In order to achieve minimum energy operation of LSI, we propose a built-in body biasing technique which generates independent body biases for nMOSFET and pMOSFET separately. We design and fabricate an application circuit integrated with our proposed built-in body bias generation (BBG) circuits in a 65-nm process. The application circuit consists of AES cipher and decipher modules. The BBG does not require an external supply and it is compatible with a dynamic voltage scaling scheme for the application circuit. Cell-based design of the BBG circuit has been applied to facilitate automatic place and route. Both of the AES and the BBG circuits have been routed simultaneously to reduce design and area overhead. In post-silicon, supply voltage and body bias voltages are selected to achieve the minimum energy consumption for a target frequency. From the measurement results, more than 20% of energy reduction is achieved compared with adjusting supply voltage alone.
@inproceedings{Kamae2015-et,title={Energy reduction by built-in body biasing with single supply voltage operation},booktitle={16th International Symposium on Quality Electronic Design},author={Kamae, Norihiro and Islam, Mahfuzul and Tsuchiya, Akira and Ishihara, Tohru and Onodera, Hidetoshi},publisher={ieeexplore.ieee.org},pages={181--185},month=mar,year={2015},}
2014
J-4
JJAP
Area-efficient reconfigurable ring oscillator for device and
circuit level characterization of static and dynamic variations
Accurate characterization of transistor variation under dynamic
switching condition has become important for reliable digital
circuit design. This paper proposes a reconfigurable ring
oscillator (RO) structure which enables measurement of
transistor level variation. Each inverter stage in the RO can be
configured into several delay modes. The delay of a particular
inverting stage can be made dominant by configuring an
inhomogeneous RO structure. By scanning the inhomogeneous stage,
delay variation of each stage can be measured. Furthermore,
pMOSFET and nMOSFET variation can be measured separately by
making only rise or fall delay dominant. Specific transistor
with random telegraph noise (RTN) in the inhomogeneous stage can
be identified by reconfiguring the inhomogeneous stage. Thus,
using a single RO, static delay variation as well as dynamic
variation such as RTN can be measured. The area for a 127-staged
reconfigurable RO including peripheral circuits is only 0.0085
mm2 thus area-efficient measurement becomes possible.
Measurement results from a 65-nm test chip shows the validity of
the proposed circuit structure.
@article{Mahfuzul_Islam2014-pp,title={Area-efficient reconfigurable ring oscillator for device and
circuit level characterization of static and dynamic variations},author={Islam, Mahfuzul and Onodera, Hidetoshi},journal={Japanese Journal of Applied Physics},publisher={IOP Publishing},volume={53},number={4S},pages={04EE08},month=mar,year={2014},language={en}}
C-14
A-SSCC
Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring
Mahfuzul
Islam, Jun
Shiomi
, Tohru
Ishihara
, and Hidetoshi
Onodera
In IEEE Asian Solid-State Circuits Conference , Mar 2014
Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leakage current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. An estimation method of threshold voltage variation is then developed. Cell-base design approach is taken so that design cost is minimized. Measurement results from a 65-nm test chip show the validity of the proposed circuit. Total area is 4500 μm 2 and active power consumption is 50 nW at 1.0 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as testing and post-silicon tuning.
@inproceedings{Islam2014Variation,author={Islam, Mahfuzul and Shiomi, Jun and Ishihara, Tohru and Onodera, Hidetoshi},booktitle={IEEE Asian Solid-State Circuits Conference},title={Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring},year={2014},pages={45--48},keywords={MOSFET circuits;Leakage currents;Monitoring;Temperature sensors;Temperature measurement;Delays;Inverters},doi={10.1109/ASSCC.2014.7008856}}
C-13
A-SSCC
A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation
A body bias generator (BBG) for fine-grain body biasing (FGBB) that can operate under wide supply-range is proposed. While FGBB is effective in reducing variability and power consumption, a number of BBGs are required on a die and therefore simplified design of BBGs is necessary. This paper proposes a cell-based design of a BBG that generates forward and reverse body bias voltages only from a core supply voltage ranging from the near threshold of 500mV to the nominal voltage of 1.2V. This wide operating range is achieved by a low voltage error amplifier with a Vth biasing scheme achieved by internal switched-capacitor charge pumping. We fabricated the forward/reverse BBG in a 65nm low power CMOS process to control 0.22mm2 of core circuit with the area overhead of 2.3% for the BBG.
@inproceedings{Kamae2014-wk,google_scholar_id={JV2RwH3_ST0C},title={A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation},booktitle={{IEEE} Asian {Solid-State} Circuits Conference},author={Kamae, Norihiro and Islam, Mahfuzul and Tsuchiya, Akira and Onodera, Hidetoshi},publisher={ieeexplore.ieee.org},pages={53--56},month=nov,year={2014},}
C-12
VLSI-DAT
Characterization and compensation of performance variability using on-chip monitors
Mahfuzul
Islam, and Hidetoshi
Onodera
In International Symposium on VLSI Design, Automation and Test , Apr 2014
Aggressive technology scaling and strong demand for lowering supply voltage impose a serious challenge in achieving robust and energy-efficient circuit operation. This paper first overviews circuit techniques for variability resilience including on-chip circuits for performance and variability monitoring. We then focus on on-chip delay cells for transistor performance estimation and homogeneous and inhomogeneous ring oscillators for Die-to-Die (D2D) and Within-Die (WID) variability extraction. We also explain topology-reconfigurable on-chip monitors for in-situ variability characterization which can be used for D2D and WID variability modeling. The monitor can also be used for monitoring temporal variability such as Random Telegraph Noise (RTN). Compensation of performance variability can be done by a localized body biasing with on-chip monitors. A proof-of-concept circuit fabricated in a 65 nm process will be demonstrated such that a test chip fabricated at the slow process corner can achieve a target performance under the typical process condition by the compensation.
@inproceedings{Islam2014-md,title={Characterization and compensation of performance variability using on-chip monitors},booktitle={International Symposium on {VLSI} Design, Automation and Test},author={Islam, Mahfuzul and Onodera, Hidetoshi},publisher={ieeexplore.ieee.org},pages={1--4},month=apr,year={2014},}
C-11
ICMTS
In-situ variability characterization of individual transistors using topology-reconfigurable ring oscillators
Mahfuzul
Islam, and Hidetoshi
Onodera
In International Conference on Microelectronic Test Structures , Mar 2014
We propose a variability characterization methodology using a topology-reconfigurable ring oscillator (RO) which enables in-situ characterization of individual transistors in the RO. By configuring the topology-reconfigurable RO into several nMOSFET and pMOSFET-sensitive topologies, local variation of each of the MOSFETs can be estimated. Measurement and estimation results from a 65 nm test chip confirm the validity of our proposed technique. We have successfully characterized static variation as well as RTN induced threshold voltage fluctuation of individual transistors. The proposed methodology can be used for fast and accurate characterization of variability.
@inproceedings{Mahfuzul_Islam2014-mt,title={In-situ variability characterization of individual transistors using topology-reconfigurable ring oscillators},booktitle={International Conference on Microelectronic Test Structures},author={Islam, Mahfuzul and Onodera, Hidetoshi},publisher={ieeexplore.ieee.org},pages={121--126},month=mar,year={2014},}
C-10
TAU
Cell-based Physical Design Automation for Analog and Mixed Signal Application
@inproceedings{Kamae2014Cell,title={Cell-based Physical Design Automation for Analog and Mixed Signal Application},booktitle={ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems},author={Kamae, Norihiro and Islam, Mahfuzul and Tsuchiya, Akira and Onodera, Hidetoshi},month=mar,year={2014}}
2013
J-3
IEICE
On-chip detection of process shift and process spread for post-silicon diagnosis and model-hardware correlation
Mahfuzul
Islam, and Hidetoshi
Onodera
IEICE Transactions on Information and Systems, Sep 2013
This paper proposes the use of on-chip monitor circuits to detect process shift and process spread for post-silicon diagnosis and model-hardware correlation. The amounts of shift and spread allow test engineers to decide the correct test strategy. Monitor structures suitable for detection of process shift and process spread are discussed. Test chips targeting a nominal process corner as well as 4 other corners of “slow-slow”, “fast-fast”, “slow-fast” and “fast-slow” are fabricated in a 65nm process. The monitor structures correctly detects the location of each chip in the process space. The outputs of the monitor structures are further analyzed and decomposed into the process variations in threshold voltage and gate length for model-hardware correlation. Path delay predictions match closely with the silicon values using the extracted parameter shifts. On-chip monitors capable of detecting process shift and process spread are helpful for performance prediction of digital and analog circuits, adaptive delay testing and post-silicon statistical analysis.
@article{Islam2013-dw,google_scholar_id={Tyk-4Ss8FVUC},title={On-chip detection of process shift and process spread for post-silicon diagnosis and model-hardware correlation},author={Islam, Mahfuzul and Onodera, Hidetoshi},journal={IEICE Transactions on Information and Systems},publisher={Institute of Electronics, Information and Communications Engineers (IEICE)},volume={E96.D},number={9},pages={1971--1979},month=sep,year={2013},}
J-2
TSM
Inhomogeneous Ring Oscillator for Within-Die Variability and RTN Characterization
This paper discusses the concept of an inhomogeneous structure for a ring oscillator (RO) to enhance the delay effect of a particular inverter stage. The frequency of the proposed inhomogeneous structure becomes a strong function of the inhomogeneous stage; thus, the variability becomes directly visible. With careful design of the inhomogeneous stage, the RO frequency can be made sensitive to a small set of transistors for characterizing transistor-by-transistor variability. Performance sensitivities of the transistors are enhanced more than 100 times that of other transistors in the RO. The proposed ROs are embedded into a 65-nm RO-array test structure, and it is verified that these ROs are highly sensitive to within-die local variability and random telegraph noise (RTN). The within-die local variability is then successfully decomposed into threshold voltage and gate length variations. Several characteristics of RTN have been successfully extracted with the proposed structure. The proposed structure is thus very useful for observation, characterization and modeling of static and dynamic transistor variations during switching operation.
@article{Fujimoto2013-po,google_scholar_id={zYLM7Y9cAGgC},title={Inhomogeneous Ring Oscillator for {Within-Die} Variability and {RTN} Characterization},author={Fujimoto, Shuuichi and Islam, Mahfuzul and Matsumoto, Takashi and Onodera, Hidetoshi},journal={IEEE Transactions on Semiconductor Manufacturing},publisher={IEEE},volume={26},number={3},pages={296--305},month=aug,year={2013},}
C-9
A-SSCC
Reconfigurable delay cell for area-efficient implementation of on-chip MOSFET monitor schemes
Mahfuzul
Islam, Tohru
Ishihara
, and Hidetoshi
Onodera
In IEEE Asian Solid-State Circuits Conference , Nov 2013
To measure target MOSFET variation, specific monitor schemes are required. With device scaling, developing each monitor scheme is costly. This paper proposes a universal delay monitor cell which enables measurements of various types of variations with single monitor scheme. The monitor cell is reconfigurable and standard cell compatible; thus it can be used in the conventional place and route flow. An area-efficient monitor scheme to monitor global, local, and dynamic variations is developed. Measurement results from a 65-nm test chip shows the validity of the proposed monitor cell. The proposed cell enables area-efficient and low cost implementation of monitor schemes which can be integrated with application such as testing and adaptive voltage scaling.
@inproceedings{Islam2013-si,title={Reconfigurable delay cell for area-efficient implementation of on-chip {MOSFET} monitor schemes},booktitle={{IEEE} Asian {Solid-State} Circuits Conference},author={Islam, Mahfuzul and Ishihara, Tohru and Onodera, Hidetoshi},publisher={ieeexplore.ieee.org},pages={125--128},month=nov,year={2013},}
C-8
SASIMI
Energy-efficient Dynamic Voltage and Frequency Scaling by P/N-performance Self-adjustment using Adaptive Body Bias
@inproceedings{Islam2013Energy,title={Energy-efficient Dynamic Voltage and Frequency Scaling by P/N-performance Self-adjustment using Adaptive Body Bias},booktitle={Workshop on Synthesis And System Integration of Mixed Information technologies},author={Islam, Mahfuzul and Kamae, Norihiro and Ishihara, Tohru and Onodera, Hidetoshi},month=oct,year={2013}}
C-7
SSDM
Area-efficient Reconfigurable Ring Oscillator for Characterization of Static and Dynamic Variations
Mahfuzul
Islam, and Hidetoshi
Onodera
In International Conference on Solid State Devices and Materials , Oct 2013
@inproceedings{Mahfuzul2013Area,title={Area-efficient Reconfigurable Ring Oscillator for Characterization of Static and Dynamic Variations},booktitle={International Conference on Solid State Devices and Materials},author={Islam, Mahfuzul and Onodera, Hidetoshi},year={2013},}
2012
J-1
TSM
Variation-sensitive monitor circuits for estimation of global process parameter variation
This paper proposes a set of monitor circuits to estimate global process variations in post-silicon. Ring oscillators (ROs) are chosen as monitor circuits where ROs are designed to have enhanced sensitivities to process variations. The proposed technique extracts process parameter variations from RO outputs. An iterative estimation method is also developed to estimate variations correctly under the presence of nonlinearity in RO outputs to process variations. Simulation results show that the proposed circuits are robust against uncertainties such as measurement error. A test chip in a 65-nm process has been fabricated to validate the circuits. Process parameter variations are successfully estimated and verified by applying body bias to the chip. The proposed technique can be used for post-silicon compensation techniques and model-to-hardware correlation.
@article{Mahfuzul2012-mk,google_scholar_id={d1gkVwhDpl0C},title={Variation-sensitive monitor circuits for estimation of global process parameter variation},author={Islam, Mahfuzul and Tsuchiya, Akira and Kobayashi, Kazutoshi and Onodera, Hidetoshi},journal={IEEE Transactions on Semiconductor Manufacturing},publisher={ieeexplore.ieee.org},volume={25},number={4},pages={571--580},month=nov,year={2012},}
C-6
ATS
On-Chip Detection of Process Shift and Process Spread for Silicon Debugging and Model-Hardware Correlation
This paper proposes the use of ROs (Ring Oscillators) for process shift and process spread detection for silicon debugging and model-hardware correlation. ROs are designed to be sensitive to either nMOSFET orpMOSFET variation, thus the location of the chip in the process spacecan be detected directly from the RO measurements. Test chip measurements in a 65-nm process shows the validity of the proposed ROs. Amounts of process shift and process spread for key process parameters as threshold voltages and gate length are extracted from test chip measurements.
@inproceedings{Mahfuzul2012-us,title={On-Chip Detection of Process Shift and Process Spread for Silicon Debugging and Model-Hardware Correlation},booktitle={{IEEE} Asian Test Symposium},author={Islam, Mahfuzul and Onodera, Hidetoshi},publisher={ieeexplore.ieee.org},pages={350--354},month=nov,year={2012},}
C-5
A-SSCC
A built-in self-adjustment scheme with adaptive body bias using P/N-sensitive digital monitor circuits
Mahfuzul
Islam, N
Kamae
, T
Ishihara
, and
others
In IEEE Asian Solid-State Circuits Conference , Nov 2012
This paper proposes a built-in self-adjustment scheme to adjust pMOSFET and nMOSFET performances to their target values. Independent control of MOSFET performances can boost circuit performance without large leakage overhead. All-digital monitor circuits have been developed to detect pMOSFET and nMOSFET variations. The scheme has been fabricated in a 65 nm process. Measurement results from corner chips confirm the validity of the scheme. At 0.7 V operation, more than 50% of circuit speed degradation has been recovered. The proposed scheme achieves 2.6 times leakage saving than the conventional critical path delay based scheme. The scheme is suitable for typical-case design and yield enhancement.
@inproceedings{Mahfuzul2012-yw,google_scholar_id={UeHWp8X0CEIC},title={A built-in self-adjustment scheme with adaptive body bias using {P/N-sensitive} digital monitor circuits},booktitle={IEEE Asian Solid-State Circuits Conference},author={Islam, Mahfuzul and Kamae, N and Ishihara, T and {others}},publisher={ieeexplore.ieee.org},year={2012},}
C-4
ICMTS
Inhomogeneous ring oscillator for WID variability and RTN characterization
We propose an inhomogeneous ring oscillator (RO) whose performance is strongly influenced by a small set of transistors for characterizing transistor-by-transistor variability. Performance sensitivities of the transistors are enhanced by inserting a "singular point" into a homogeneous RO. Proposed ROs have been embedded in a 65nm RO-array test structure, and it is verified that the proposed ROs are highly sensitive to Within-Die (WID) local variability and Random Telegraph Noise (RTN). The amounts of random variation in threshold voltages(VthN and VthP ) and channel length(L) are extracted from the WID frequency variation. Temporal variation of oscillation frequency due to RTN is observed in the inhomogeneous RO.
@inproceedings{Fujimoto2012Inhomogeneous,google_scholar_id={u-x6o8ySG0sC},author={Fujimoto, Shuichi and Islam, Mahfuzul and Matsumoto, Takashi and Onodera, Hidetoshi},booktitle={IEEE International Conference on Microelectronic Test Structures},title={Inhomogeneous ring oscillator for WID variability and RTN characterization},year={2012},pages={25--30},keywords={Nonhomogeneous media;Semiconductor device measurement;MOS devices;Sensitivity;MOSFET circuits;Frequency measurement;Logic gates},doi={10.1109/ICMTS.2012.6190607},}
2011
C-3
ICMTS
Variation-sensitive monitor circuits for estimation of Die-to-Die process variation
We propose a set of variation-sensitive ring oscillators (RO) to estimate Die-to-Die process parameter variation. ROs are designed to have different sensitivity to each parameter variation. A method suitable to estimate variation from different ROs is proposed. We have fabricated test chip and successfully estimated process parameter variation. Variation results are correlated with that in Process Control Module data.
@inproceedings{Mahfuzul2011-sx,google_scholar_id={u5HHmVD_uO8C},title={Variation-sensitive monitor circuits for estimation of {Die-to-Die} process variation},booktitle={{IEEE} International Conference on Microelectronic Test Structures},author={Islam, Mahfuzul and Tsuchiya, Akira and Kobayashi, Kazutoshi and Onodera, Hidetoshi},publisher={IEEE},pages={153--157},month=apr,year={2011},}
2010
C-2
DFM&Y
Extraction of variability sources from within-die random delay variation
Characterization and modeling of delay variability on a real silicon is key topic for statistical timing analysis. In this paper, we propose a method of extracting variability information from a real silicon. We have measured WID delay variability in 65nm process using RO-array test structures, and discuss how to separate random component into the variability of threshold voltage and channel length.
@inproceedings{Fujimoto2010Component,title={Extraction of variability sources from within-die random delay variation},booktitle={IEEE International Workshop on Design for Manufacturability & Yield},author={Fujimoto, Shuuichi and Islam, Mahfuzul and Nishizawa, Shinichi and Onodera, Hidetoshi},month=may,year={2010}}
C-1
TAU
Process-sensitive monitor circuits for estimation of die-to-die process variability
In this paper, we propose a set of ring oscillators (ROs) to estimate D2D variation of MOS threshold voltage and gate length. First, we show a design guideline on designing ROs with enhanced process sensitivities. We propose a set of ROs for process parameter estimation. We then develop an estimation method using a linear model to extract the variations from the measured frequencies. Simulation results conØrm that our proposed circuits are able to extract process parameters in the conditions of error in the measurement. We build test chips to conØrm the validity of our proposed ROs. We extracted process parameter variation using our monitor circuits. Variation results satisfy the variation range in Process Control Module (PCM) data and are within the corner model. The proposed ROs can be built on-chip to monitor process parameter variation in real time.
@inproceedings{Mahfuzul2010-lj,title={Process-sensitive monitor circuits for estimation of die-to-die process variability},booktitle={{ACM} International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems},author={Islam, Mahfuzul and Tsuchiya, Akira and Kobayashi, Kazutoshi and Onodera, Hidetoshi},pages={83--85},year={2010},}
Awards
By students
Best Paper Award, 35th IEEE International Conference on Microelectronic Test Structures, March 2023
Yuma Iwata
Paper: Measurement of temperature effect on comparator offset voltage variation
Best Design Award, ASP-DAC University Design Contest, January 2023
Shun Yamaguchi
Paper: A fully synchronous digital LDO with built-in adaptive frequency modulation and implicit dead-zone control
